The present invention relates to a semiconductor memory device, and more particularly, to example embodiments of a memory cell structure that can maximize the separation spacing between closest adjacent memory elements for a given memory cell size.
A semiconductor memory device normally comprises an array of memory cells, each of which includes a memory element and a selection transistor coupled in series between two electrodes. The selection transistor functions like a switch to direct current or voltage through the selected memory element coupled thereto. Upon application of an appropriate voltage or current to the memory element, the electrical property of the memory element would change accordingly, thereby switching the stored logic in the respective memory cell.
A semiconductor memory device may be either volatile or non-volatile, depending on the type of memory element and the memory architecture employed. An example of volatile memory device is dynamic random access memory (DRAM), which loses its stored information when power is interrupted or lost. Non-volatile memory device, such as magnetic random access memory (MRAM) or other types of resistance-based memory devices, can retain stored information when powered off.
A resistance-based memory element can be classified into at least one of several known groups based on its resistance switching mechanism. The memory element of Phase Change Random Access Memory (PCRAM) may comprise a phase change chalcogenide compound, which can switch between a resistive amorphous phase and a conductive crystalline phase. The memory element of Conductive Bridging Random Access Memory (CBRAM) relies on the statistical bridging of metal rich precipitates therein for its switching mechanism. The memory element of CBRAM normally comprises a nominally insulating metal oxide material, which can switch to a lower electrical resistance state as the metal rich precipitates grow and link to form conductive paths upon application of an appropriate voltage. The memory element of Magnetic Random Access Memory (MRAM) typically comprises at least two layers of ferromagnetic materials with an insulating tunnel junction layer interposed therebetween. When a switching current is applied to the memory element of a MRAM device, one of the ferromagnetic layers will switch its magnetization direction with respect to that of the other magnetic layer, thereby changing the electrical resistance of the element.
To be cost competitive, a small memory cell size is desired in order to increase device density on wafers. One way to achieve this is to simply shrink the minimum feature size, F, normally associated with a particular manufacturing process. In memory applications where memory cells are arranged in dense and repetitive patterns, photolithography is more constrained by the pitch of the feature pattern rather than the feature size itself. This is because the feature size can be modulated by photo lithography process conditions, such as exposure and resist development, but shrinkage of the feature pitch would require shorter wavelength light source and/or significant improvement in optics. In reality, the scaling of the device size in a dense array, such as that in memory applications, is limited by the minimum feature pitch of 2F. Moreover, it is normally assumed that the minimum feature size is half of the corresponding minimum pitch. Accordingly, the minimum pitch between two repetitive features on a same mask layer would be 2F, as would be understood by one of ordinary skill in the art.
Another approach to reduce the memory cell size is to use a compact cell structure. Recent advances in semiconductor processing, such as implementation of buried gate and oblique active region, have reduced the memory cell size of DRAM to 6F2. For example, FIG. 1 is a top view that illustrates the arrangement of an array of 6F2 memory cells for a memory device as disclosed by Baek et al. in U.S. Pat. No. 8,084,801. The memory device includes a semiconductor substrate 50 and a plurality of active regions 52 formed therein. The active regions 52 have an elongated shape extending along the x-direction and are arranged in a staggered pattern along the x-direction. Each active region 52 has two source contacts 54 formed on top of the end portions thereof and a bit contact 56 disposed on the central portion thereof. For reasons of clarity, word lines in the form of buried gate and bit lines are not shown herein. Each source contact 54 has a memory element (not shown) formed thereon. In the cell layout shown in FIG. 1, each memory cell, which includes a transistor and a memory element, has a cell size of 6F2 if the center-to-center spacing between two closest neighbors of the source contacts 54 is 2F. Assuming the source contacts 54 have a diameter of about 1F, then the gap between two closest neighbors is about 1F. The memory elements, which are formed on top of the source contacts 54, are subjected to the same geometric constraint with the center-to-center spacing between two closest neighbors being 2F. For 6F2 memory cell design, such as the one shown in FIG. 1, it is desirable to increase the minimum spacing between two adjacent memory elements to increase the gap therebetween for easing processing constraints or to increase the memory size for improving memory performance or both.
For the foregoing reasons, there is a need for a 6F2 memory device that has a center-to-center spacing between adjacent memory elements greater than 2F and that can be inexpensively manufactured.